SH7763 Datasheet, PDF (913/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1)
The TSU has an alert function, which informs the E-MAC-0 and E-MAC-1 that writing to the
relay FIFO will be disabled when the data volume written in the relay FIFO during relay
operations exceeds a certain threshold. TSU_BSYSL1 sets the threshold of the relay FIFO when
the TSU alerts the E-MAC-1 that writing in the relay FIFO will be disabled during relay
operations.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










BSYSL1[5:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 6 
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 847 of 1956
REJ09B0256-0100