SH7763 Datasheet, PDF (1733/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
ADST
ADF
Consecutive A/D conversion execution
Set*
Clear*
Clear
ADI
Channel 0(AN0) Idle
A/D conversion (1)
Interrupt occurs
Idle
A/D conversion (4)
Idle
Channel 1(AN1)
Idle
A/D conversion (2)
Idle
A/D conversion (5) Idle
Channel 2(AN2)
Idle
A/D conversion (3)
Idle
Channel 3(AN3)
Idle
ADDRA
ADDRB
A/D conversion result (1)
A/D conversion result (2)
A/D conversion result (4)
A/D conversion result (5)
ADDRC
A/D conversion result (3)
ADDRD
Note: * Vertical arrows (↓) indicate instruction execution by software.
Figure 38.4 Example of A/D Converter Operation (Scan Mode,
Three Channels AN0 to AN2 Selected)
Rev. 1.00 Oct. 01, 2007 Page 1667 of 1956
REJ09B0256-0100