SH7763 Datasheet, PDF (1278/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Bit
7 to 5
4 to 0
Initial
Bit Name Value R/W
RFWM[2:0] 000
R/W
RFUA[4:0] 00000 R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of
the receive FIFO are valid.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
the receive FIFO are valid.
101: Issue a transfer request when 8 or more stages of
the receive FIFO are valid.
110: Issue a transfer request when 12 or more stages
of the receive FIFO are valid.
111: Issue a transfer request when 16 stages of the
receive FIFO are valid.
• A transfer request to the receive FIFO is issued by
the RDREQE bit in SISTR.
• The receive FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
Receive FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (empty) to B'10000 (full).
Rev. 1.00 Oct. 01, 2007 Page 1212 of 1956
REJ09B0256-0100