SH7763 Datasheet, PDF (503/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
At level 0, DDR-SDRAM controls such as DDR-SDRAM refresh and page management have the
highest priority. The memory is refreshed according to the memory refresh intervals specified
separately.
At level 1, access is rotated between access from the SHway bus and access from the LCDC (in
round-robin method). However, immediately after a reset, access from the SHwy bus has priority
over access from the LCDC.
Access is not arbitrated based on the order of requests but by a request signal that is asserted
between transactions. When read and write requests are made for the same device simultaneously,
a read request has priority. Access arbitration is performed between transactions.
(2) Access Arbitration When Burst and Non-Burst Transfers Coexist
The arbiter block receives inputs from the SHwy bus with the 133*¹ MHz interface and the LCDC
with the 66*² MHz interface. Therefore, arbitration operation differs depending on a burst and
non-burst transfers
• In burst transfers, an arbitrated module can perform continuous transfers. Therefore, the SHwy
bus and the LCDC have the same possibility of being arbitrated.
• In non-burst transfers, arbitration is performed in 133*¹ MHz units. Requests are continuously
output to the DDRC.
However, in actuality, burst and non-burst transfers coexist. Signals output from the interfaces are
used to determine whether a burst transfer is expected or not. When making arbitration from non-
burst transfers to burst transfers, if the arbitrated transaction is a burst transfer, the non-burst
transfer is continued after the burst transfer.
Notes: 1. This indicates the clock frequency when DDR266-SDRAM is used. The clock
frequency is 100 MHz when DDR200-SDRAM is used.
2. This indicates the clock frequency when DDR266-SDRAM is used. The clock
frequency is 50 MHz when DDR200-SDRAM is used.
12.5.14 Coherency When Accessing DDR-SDRAM
In some cases, writing the DDR-SDRAM via the SHwy bus by software may be held for some
reason and reading the DDR-SDRAM by the subsequently activated LCDC may be executed first.
That is, incorrect operation may occur if coherency for accessing the DDR-SDRAM is not
guaranteed.
In this case, execute the SYNCO instruction between the write instruction for the DDR-SDRAM
by software and the LCDC activation instruction. When the SYNCO instruction is executed, the
next instruction is not activated until the data access being performed is completed.
Rev. 1.00 Oct. 01, 2007 Page 437 of 1956
REJ09B0256-0100