SH7763 Datasheet, PDF (1722/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
Figure 38.1 shows a block diagram of the A/D converter.
Peripheral data bus
AVcc
AVss
10-bit
D/A
Internal
data bus
AN0
+
AN1
Analog
AN2
multi-
plexer
AN3
–
Comparator
Control circuit
Sample-and-
hold circuit
Pck0/4
Pck0/8
Pck0/16
Pck0/32
A/D converter
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 38.1 Block Diagram of A/D Converter
Peripheral
Clock (Pck0)
ADI
interrupt
signal
Rev. 1.00 Oct. 01, 2007 Page 1656 of 1956
REJ09B0256-0100