SH7763 Datasheet, PDF (435/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
(2) Wait Cycle Control
Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits for
each area in CSnWCR is not 0, a software wait is inserted in accordance with the wait-control bits.
For details, see section 11.4.4, CSn Wait Control Register (CSnWCR).
A specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR
setting. The insertion timing of the wait cycle is shown in figure 11.8.
CLKOUT
A25 to A0
CSn
RDWR
T₁
T_w
T₂
RD
D31 to D0
(read)
WE
D31 to D0
(Write)
BS
RDY
DACK
(DA)
DA: Dual address DMA
Figure 11.8 SRAM Interface Wait Timing (Software Wait Only)
Rev. 1.00 Oct. 01, 2007 Page 369 of 1956
REJ09B0256-0100