SH7763 Datasheet, PDF (1668/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
37.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image
recognized by the graphics driver. This register specifies how many bytes the address from which
data is to be read should be moved when the Y coordinates have been incremented by 1. This
register does not have to be equal to the horizontal width of the LCD panel. When the memory
address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register
becomes equal to B in this equation.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LAO[15:0]
Initial value: 0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
LAO
H'0280
R/W
[15:0]
Description
Line Address Offset
The minimum alignment unit of LDLAOR is 16 bytes.
Because the LCDC handles these values as 16-byte
data, the values written to the lower four bits of the
register are always treated as 0. The lower four bits of
the register are always read as 0. The initial values (×
resolution = 640) will continuously and accurately
place the VGA (640 × 480 dots) display data without
skipping an address between lines. For details, see
table 37.5.
A binary exponential at least as large as the horizontal
width of the image is recommended for the LDLAOR
value, taking into consideration the software operation
speed. When the hardware rotation function is used,
the LDLAOR value should be a binary exponential (in
this example, 256) at least as large as the horizontal
width of the image (after rotation, it becomes 240 in a
240 × 320 panel) instead of the horizontal width of the
LCD panel (320 in a 320 × 240 panel).
Rev. 1.00 Oct. 01, 2007 Page 1602 of 1956
REJ09B0256-0100