SH7763 Datasheet, PDF (528/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(3) PCI Command Register (PCICMD)
The PCI command register provides coarse control over a device's ability to generate and respond
to PCI cycles. When 0 is written to this register, the device is logically disconnected from the PCI
bus for all accesses except configuration accesses.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





 FBBE SERRE WCC PER VGAPS MWIE SC BM MS IOS
Initial value: 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
SH R/W: R R R R R R R R/W R/W R/W R R R R/W R/W R/W
PCI R/W: R R R R R R R R/W R/W R/W R R R R/W R/W R/W
Bit
Bit Name
15 to 10 
9
FBBE
8
SERRE
7
WCC
Initial
Value
All 0
0
0
1
R/W
Description
SH: R Reserved
PCI: R
These bits are always read as 0. The write value
should always be 0.
SH: R PCI Fast Back-to-Back Enable
PCI: R
Controls whether or not a master can do fast back-to-
back transactions to different device.
0: Fast back-to-back transactions are only allowed to
the same target
1: Master is allowed to generate fast back-to-back
transactions to different targets (not supported)
SH: R/W PCI SERR Output Control
PCI: R/W Controls the SERR output.
0: SERR output disabled
1: SERR output enabled
SH: R/W Wait Cycle Control
PCI: R/W Controls the address/data stepping.
When WCC = 1, both an address and data for a master
write, only an address for a master read, and only data
for a target read are output for at least two clock cycles.
0: Address/data stepping control disabled
1: Address/data stepping control enabled
Rev. 1.00 Oct. 01, 2007 Page 462 of 1956
REJ09B0256-0100