SH7763 Datasheet, PDF (1157/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.14 Serial Error Register (SCRER)
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR.
SCRER can always be read from the CPU.
BIt: 15

Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
 PER5 PER4 PER3 PER2 PER1 PER0 
0
0
0
0
0
0
0
0
RRRRRRRR
6
5
4
3
2
1
0
 FER5 FER4 FER3 FER2 FER1 FER0
0
0
0
0
0
0
0
RRRRRRR
Bit
15, 14
Bit Name
—
Initial
Value
All 0
13
PER5
0
12
PER4
0
11
PER3
0
10
PER2
0
9
PER1
0
8
PER0
0
7, 6
—
All 0
5
FER5
0
4
FER4
0
3
FER3
0
2
FER2
0
1
FER1
0
0
FER0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
Number of Parity Errors
R
These bits indicate the number of data bytes in which a
R
parity error occurred in the receive data stored in
SCFRDR.
R
After the ER bit in SCFSR is set, the value indicated by
R
bits PER5 to PER0 is the number of data bytes in which
R
a parity error occurred.
If all 64 bytes of receive data in SCFRDR have parity
errors, the value indicated by bits PER5 to PER0 will be
0.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
Number of Framing Errors
R
These bits indicate the number of data bytes in which a
R
framing error occurred in the receive data stored in
SCFRDR.
R
After the ER bit in SCFSR is set, the value indicated by
R
bits FER5 to FER0 is the number of data bytes in which
R
a framing error occurred.
If all 64 bytes of receive data in SCFRDR have framing
errors, the value indicated by bits FER5 to FER0 will be
0.
Rev. 1.00 Oct. 01, 2007 Page 1091 of 1956
REJ09B0256-0100