SH7763 Datasheet, PDF (513/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
T0 T1
T0 T1
REFS
REFSX
*¹
t_XSNR/t_XSRD*²
Any
Command
MCS
MRAS
MCAS
MWE
Self-refresh
Notes: 1. This timing should satisfy the conditions specified by the DDR-SDRAM used when driving CKE high.
2. This timing should satisfy the conditions specified by the DDR-SDRAM used.
(tXSNR is for a non-READ command and tXSRD is for a READ command;
tXSRD should usually be 200 clock cycles or longer.)
Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/Self-Refresh
Exit (REFSX) to Any Command Input)
Rev. 1.00 Oct. 01, 2007 Page 447 of 1956
REJ09B0256-0100