SH7763 Datasheet, PDF (607/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(5) Exclusive Access
The lock access on the PCI bus is supported.
When the PCI local bus is locked, the PCIC is accessible from the device that activates the LOCK
signal.
SuperHyway bus resource lock does not occur. (Another on-chip module can access the PCIC
during a lock transfer.)
(6) Endian
This LSI supports both the big and little endian formats. Since the PCI local bus is inherently little
endian, the PCIC supports both byte swapping and non-byte swapping.
The endian format is specified by the setting of the TBS bit in the PCI control register (PCICR).
Note: In the following figures, “MSByte” means the most significant byte and “LSByte” means
the least significant byte.
Rev. 1.00 Oct. 01, 2007 Page 541 of 1956
REJ09B0256-0100