SH7763 Datasheet, PDF (693/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU)
15.4 Operation
With this LSI, a CPU externally connected to the LSI (an external CPU) is allowed to access the
DDR-SDRAM space or internal registers of the LSI by using the MPX protocol.
The external CPU becomes ready to access the space in this LSI after this sequence: an access
request (BREQ) from the external CPU is accepted by the LBSC, the local bus is released, and an
access acknowledgement (BACK) is returned to the external CPU.
The EXCPU determines whether the access is to the DDR-SDRAM space or to an internal register
according to the CS signals (EX_CS0, EX_CS1) from the external CPU and performs processing
for the respective access.
In the case of access to the DDR-SDRAM space, the EXCPU implements access to the DDR-
SDRAM space in this LSI by converting the signal from the external CPU from the MPX protocol
to the SuperHyway bus protocol. In this process, data alignment conversion is performed with the
same endian as this LSI according to the access size from the external CPU.
(1) Space Accessible to the External CPU
The DDR-SDRAM space and internal registers of this LSI are accessible to the external CPU. The
space to be accessed is selected as shown below using the CS signals.
• EX_CS0:
• EX_CS1:
DDR-SDRAM space (64 Mbytes)
Internal registers of this LSI
For DDR-SDRAM space access, however, the size of the space that can be accessed by the
external CPU is 64 Mbytes while the entire DDR-SDRAM space in this LSI is 512 Mbytes. So,
access to the entire DDR-SDRAM space from the external CPU is enabled by the window
method. To access the entire DDR-SDRAM space in this LSI, first designate a 64-Mbyte access
space by the EXCMSETR register of the EXCPU, and then create an access to the DDR-SDRAM
space.
Rev. 1.00 Oct. 01, 2007 Page 627 of 1956
REJ09B0256-0100