SH7763 Datasheet, PDF (314/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
22
IRLM1
0
21 to 0 
All 0
R/W Description
R/W IRL Pin Mode 1
Selects whether IRQ7/IRL7 to IRQ4/IRL4 are used as
the 4-bit encoded interrupt requests or as four
independent interrupts.
0: IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit level-
encoded interrupt requests (IRL [7:4] interrupt; initial
value)
1: IRQ7/IRL7 to IRQ4/IRL4 are used as four
independent interrupt requests (IRQ [n] interrupt; n
= 7 to 4)
Note: The level-encoded IRL interrupt is not detected
unless the pin levels sampled at every bus
clock cycle remain unchanged for four
consecutive cycles.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9.3.2 Interrupt Control Register 1 (ICR1)
ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection
modes of external interrupt input pins IRQ7/IRL7 to IRQ4/IRL4. This setting is valid only when
using IRL7 to IRL4 and IRL3 to IRL0 as IRQ independent interrupts input to set the IRLM0 and
IRLM1 bits to 1 in ICR0.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30
IRQ0S
29 28
IRQ1S
27 26
IRQ2S
25 24
IRQ3S
23 22
IRQ4S
21 20
IRQ5S
19 18
IRQ6S
17 16
IRQ7S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− −−−−− −−−−− − −−−−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Rev. 1.00 Oct. 01, 2007 Page 248 of 1956
REJ09B0256-0100