SH7763 Datasheet, PDF (101/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Pin No. Pin Name
AD17 PTO0/AUDSYNC/
RMII1_MDC/SSI2_WS
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AE1
AE2
AE3
PTO4/AUDATA3/EX_INT/
SSI3_WS
ASEBRK/BRKACK
VSS-PLL3
VSS-PLL2
BREQ
VCCQ
VSS-PLL1
AVcc
VSSQ
VCCQ
PTG5/GNT3/ET1_RX-CLK
AE4 PTH5/AD23/TPU_TO1/
ET1_ERXD1/RMII1M_TXD0
AE5 PTH4/AD19/TPU_TO0/
ET1_ERXD3/RMII1M_RXD0
AE6
PTD1/CBE2/PCC_VS2/
SIOF0_TXD/HAC_SD_OUT/
LCDM_D15
AE7
PTA1/DEVSEL/SCIF1_RXD
AE8
PTB0/PERR/PINT8/
LCDM_D10
AE9 PTB4/CBE1/PINT12/
LCDM_D8
AE10 PTA5/AD12
I/O
IO/O/O/IO
IO/O/O/IO
IO


I





IO/O/I
IO/IO/O/I/O
IO/IO/O/I/I
IO/IO/I/O/O/O
IO/IO/I
IO/IO/I/O
IO/IO/I/O
IO/IO
Function
Power
Supply
Port/AUD sync signal/RMII
management data clock/SSI word
select
VCCQ
Port/AUD data/external CPU
interrupt/SSI word select
VCCQ
Break mode acknowledge
VCCQ
PLL3 GND

PLL2 GND

Bus release request
VCCQ
I/O VCC

PLL1 GND

Analog VCC

I/O GND

I/O VCC

Port/PCI bus grant/ETHER receive VCCQ
clock
Port/PCI address-and-data bus/TPU VCCQ
clock output/ETHER receive
data/RMII transmit data (mirror pin)
Port/PCI address-and-data bus/TPU VCCQ
clock output/ETHER receive
data/RMII receive data (mirror pin)
Port/PCI command-and-byte
enable/PCMCIA VS2/SIOF transmit
data/HAC serial data output/LCD
data (mirror pin)
VCCQ
Port/PCI device select/SCIF receive VCCQ
data
Port/PCI system error/port interrupt VCCQ
input/LCD data (mirror pin)
Port/PCI command-and-byte
enable/port interrupt input/LCD data
(mirror pin)
VCCQ
Port/PCI address-and-data bus
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 35 of 1956
REJ09B0256-0100