SH7763 Datasheet, PDF (1724/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
38.3 Register Descriptions
Table 38.2 shows the ADC register configuration. Table 38.3 shows the register state in each
operating mode.
Table 38.2 Register Configuration
Register Name
Abbreviation R/W
Area P4
Address*
Area 7
Address*
Access
Size
A/D data register A
ADDRA
R
H'FFEA 0000 H'1FEA 0000 16
A/D data register B
ADDRB
R
H'FFEA 0002 H'1FEA 0002 16
A/D data register C
ADDRC
R
H'FFEA 0004 H'1FEA 0004 16
A/D data register D
ADDRD
R
H'FFEA 0006 H'1FEA 0006 16
A/D control/status register ADCSR
R/W H'FFEA 0010 H'1FEA 0010 16
Note: * P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
Table 38.3 Register State in Each Operating Mode
Register Name
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D control/status register
Power-On
Abbreviation Reset
ADDRA
H'0000
ADDRB
H'0000
ADDRC
H'0000
ADDRD
H'0000
ADCSR
H'0000
Manual
Reset
H'0000
H'0000
H'0000
H'0000
H'0000
Sleep
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
38.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are always read as 0.
Table 38.4 indicates the pairings of analog input channels and A/D data registers.
Rev. 1.00 Oct. 01, 2007 Page 1658 of 1956
REJ09B0256-0100