SH7763 Datasheet, PDF (116/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
<Big endian>
63
0
Floating-point register
DR (2i)
63
FR (2i)
0
FR (2i+1)
63
Memory area
8n
32 31
0
8n+3 8n+4 8n+7
<Little endian>
63
0
Floating-point register
DR (2i)
*1, *2
63
0
FR (2i) FR (2i+1)
63
0
DR (2i)
*2
63
0
FR (2i)
FR (2i+1)
63
0
DR (2i)
63
FR (2i)
0
FR (2i+1)
63
Memory area
4n+3
32 31
0 63
32 31
0 63
32 31
0
4n 4m+3
(1) SZ = 0
4m 8n+3
8n 8n+7 8n+4 8n+7 8n+4 8n+3 8n
(2) SZ = 1, PR = 0
(3) SZ = 1, PR = 1
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used.
2. The bit-location of DR register is used for double precision format when PR = 1.
(In the case of (2), it is used when PR is changed from 0 to 1.)
Figure 2.5 Relationship between SZ bit and Endian
Table 2.2 Bit Allocation for FPU Exception Handling
Field Name
FPU
Invalid
Division Overflow Underflow Inexact
Error (E) Operation (V) by Zero (Z) (O)
(U)
(I)
Cause
FPU exception
cause field
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable
FPU exception
enable field
None
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag
FPU exception flag None
Bit 6
field
Bit 5
Bit 4
Bit 3
Bit 2
(5) Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined)
Information is transferred between the FPU and CPU via FPUL.
Rev. 1.00 Oct. 01, 2007 Page 50 of 1956
REJ09B0256-0100