SH7763 Datasheet, PDF (1587/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.12 Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of the IFR1. When an interrupt flag is set to 1 while the
corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the
ISR1 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
EP3 EP3 VBUSF
TR IE TS IE IE
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit
Bit Name
31 to 8 
7 to 3 
2
EP3 TR IE
1
EP3 TS IE
0
VBUSF IE
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W EP3 TR Interrupt Enable
0
R/W EP3 TS Interrupt Enable
0
R/W VBUSF Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1521 of 1956
REJ09B0256-0100