SH7763 Datasheet, PDF (1376/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.12 Interrupt Control Registers 0 and 1 (INTCR0, INTCR1)
The INTCR registers enable or disable the INTSTR0 and INTSTR1 flags and control the interrupt
outputs.
• INTCR0
Bit: 7
FEIE
Initial value: 0
R/W: R/W
6
5
4
3
2
1
0
FFIE DRPIE DTIE CRPIE CMDIE DBSYIE BTIE
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
FEIE
0
R/W FIFO Empty Flag Enable
0: Disables FIFO empty flag setting.
1. Enables FIFO empty flag setting.
6
FFIE
0
R/W FIFO Full Flag Enable
0: Disables FIFO full flag setting.
1: Enables FIFO full flag setting.
5
DRPIE
0
R/W Data Response End Flag Enable
0: Disables data response end flag setting.
1: Enables data response end flag setting.
4
DTIE
0
R/W Data Transfer End Flag Enable
0: Disables data transfer end flag setting.
1: Enables data transfer end flag setting.
3
CRPIE
0
R/W Command Response End Flag Enable
0: Disables command response end flag setting.
1: Enables command response end flag setting.
2
CMDIE
0
R/W Command Output End Flag Enable
0: Disables command output end flag setting.
1: Enables command output end flag setting.
1
DBSYIE 0
R/W Data Busy End Flag Enable
0: Disables data busy end flag setting.
1: Enables data busy end flag setting.
Rev. 1.00 Oct. 01, 2007 Page 1310 of 1956
REJ09B0256-0100