SH7763 Datasheet, PDF (359/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
When the INTMU bit in CPUOPM is 1, the interrupt mask level (IMASK) in SR is automatically
modified to the level of the accepted interrupt. When the INTMU bit is 0, the IMASK value in SR
is not affected by the accepted interrupt.
9.4.3 IRL Interrupts
IRL interrupts are input by level at pins IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to IRQ0/IRL0.
The priority level is the level indicated by pins IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to
IRQ0/IRL0. An IRQ7/IRL7 to IRQ4/IRL4 or IRQ3/IRL3 to IRQ0/IRL0 pins input are all low
level indicates the highest-level interrupt request (interrupt priority level 15), and all high level
indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL
interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt
levels.
Interrupt
request
Priprity
encoder
IRL3 to IRL0
SH7763
IRQ3/IRL3 to
IRQ0/IRL0
Interrupt
request
Priprity
encoder
IRL7 to IRL4
IRQ7/IRL7 to
IRQ4/IRL4
Figure 9.2 Example of IRL Interrupt Connection
Rev. 1.00 Oct. 01, 2007 Page 293 of 1956
REJ09B0256-0100