SH7763 Datasheet, PDF (559/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(6) PCI Interrupt Register (PCIIR)
PCIIR records the source of an interrupt.
When multiple interrupts occur, only the first source is registered.
When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this
register, however, no interrupt occurs.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
TTA
DI
—
—
—
—
TMT
OI
MDEI
APE
DI
SE
DI
DPEI DPEI TAD MAD MW MRD
TW TR IM IM PDI PEI
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R/WC R R R R R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 15 
14
TTADI
Initial
Value
All 0
0
R/W
Description
SH: R
Reserved
PCI: R
These bits are always read as 0. The write value
should always be 0.
SH: R/WC Target Target-Abort Interrupt
PCI: R
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
A target-abort is detected as an illegal byte enable
when the lower two bits (bits 1 and 0) of the address
and the byte enable do not match during an I/O
transfer (target).
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 493 of 1956
REJ09B0256-0100