SH7763 Datasheet, PDF (312/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.1 Interrupt Control Register 0 (ICR0)
ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode of
the external interrupt input pins (IRQ7/IRL7 to IRQ0/IRL0) and NMI pin, and indicates the input
level to the NMI pin.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− NMIL ^MAI − − − − ^{NMIB NMIE IRLM0 IRLM1} − − − − −
− Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R R R R/W R/W R/W R/W R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−−−− −−−− −−−− −−−−
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31
NMIL
30
MAI
29 to 26 
Initial
Value
R/W
Undefined R
0
R/W
All 0
R
Description
NMI Input Level
Sets the signal level input to the NMI pin. Reading this
bit allows the user to know the NMI pin level, and
writing is invalid.
0: Low level is input to the NMI pin
1: High level is input to the NMI pin
MAI Interrupt Mask
Specifies whether all interrupts are masked during the
low level period of the NMI pin level regardless of the
BL bit in SR of the CPU.
0: Interrupts are enabled even if the NMI pin goes low
1: Interrupts are disabled if the NMI pin goes low
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 246 of 1956
REJ09B0256-0100