SH7763 Datasheet, PDF (477/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.2 Input/Output Pins
Table 12.1 shows the DDRIF pin configuration. For details on connection with the DDR-SDRAM,
see the LSI pin information section. Note that clock-related signals will be determined later.
Table 12.1 Pin Configuration
Pin Name
M_CLK0
M_CLK1
Function
DDR-SDRAM clock
DDR-SDRAM clock
M_CKE
Clock enable
I/O
Output
Output
Output
M_CS
Chip select
M_WE
Write enable
M_A13 to M_A0
Address
M_BA1, M_BA0
Bank active
M_D31 to M_D0
Data
M_DQS3 to M_DQS0 I/O data strobe
M_DQM3 to M-DQM0 Data mask
M_RAS
Row address strobe
M_CAS
Column address strobe
M_BKPRST
Power back-up reset
Output
Output
Output
Output
I/O
I/O
Output
Output
Output
Input
M_VREF
Reference voltage input Input
Description
Clock output for DDR-SDRAM
Clock output for DDR-SDRAM
Inverted clock output of M_CLK0
When this pin goes high, the clock
signal is active. When this pin goes
low, the clock signal is inactive.
Chip select output
Write enable output
Row/column address
Bank address output
Data I/O
I/O data strobe
I/O data mask signal
Row address strobe signal
Column address strobe signal
When this pin goes low, the M_CKE
pin shall go low
Input reference voltage
Rev. 1.00 Oct. 01, 2007 Page 411 of 1956
REJ09B0256-0100