SH7763 Datasheet, PDF (1458/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
Figure 33.1 shows a block diagram of the HAC.
HAC receiver
HAC_
SD_IN (0/1)
Shift register for slot 1
Shift register for slot 2
Data[19:0]
Data[19:0]
Shift register for slot 3
Data[19:0]
Shift register for slot 4
Data[19:0]
HAC_BITCLK
Slot3, slot4
request signal
Control
signal
Bit control signal
HAC_
SD_OUT (0/1)
HAC_SYNC (0/1)
HAC_RES
HAC transmitter
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
Data[19:0]
Data[19:0]
Data[19:0]
Data[19:0]
Control
signal
Internal bus interface
(Reception)
CSAR RX buffer
CSDR RX buffer
PCML RX buffer
Data[31:0]
PCMR RX buffer
DMA control
DMA request
Interrupt request
Internal bus interface
(Transmission)
CSAR TX buffer
CSDR TX buffer
Data[31:0]
PCML TX buffer
PCMR TX buffer
DMA control
DMA request
Interrupt request
Figure 33.1 Block Diagram
33.2 Input/Output Pins
Table 33.1 describes the HAC pin configuration.
Table 33.1 Pin Configuration
Pin Name
HAC_BITCLK
HAC_SD_IN
HAC_SD_OUT
HAC_SYNC
HAC_RES
I/O
Input
Input
Output
Output
Output
Function
HAC serial data clock
HAC serial data incoming to Rx frame
HAC serial data outgoing from Tx frame
HAC frame sync
HAC reset (negative logic signal)
Rev. 1.00 Oct. 01, 2007 Page 1392 of 1956
REJ09B0256-0100