SH7763 Datasheet, PDF (731/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
(2) Manual Reset by Watchdog timer Overflowed in Sleep Mode
EXTAL
input
CLKOUT
output
WDT overflow
signal
STATUS[1:0]
output
HL (sleep)
HH (reset)
LL (normal)
WDT reset
stabilization time
WDT reset
holding time
Figure 17.9 STATUS Output by Watchdog timer overflow Manual Reset
during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 665 of 1956
REJ09B0256-0100