SH7763 Datasheet, PDF (176/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
5.4 Exception Types and Priorities
Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.3 Exceptions
Exception Transition
Direction*³
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level*² Order*² Address
Exception
Offset Code*⁴
Reset
Abort type Power-on reset
1
1
H'A000 0000 —
H'000
Manual reset
1
2
H'A000 0000 —
H'020
H-UDI reset
1
1
H'A000 0000 —
H'000
Instruction TLB multiple-hit
1
3
H'A000 0000 —
H'140
exception
Data TLB multiple-hit exception 1
4
H'A000 0000 —
H'140
General Re-
User break before instruction 2
0
(VBR/DBR) H'100/— H'1E0
exception execution execution*¹
type
Instruction address error
2
1
(VBR)
H'100 H'0E0
Instruction TLB miss exception 2
2
(VBR)
H'400 H'040
Instruction TLB protection
2
3
(VBR)
H'100 H'0A0
violation exception
General illegal instruction
2
4
(VBR)
H'100 H'180
exception
Slot illegal instruction exception 2
4
(VBR)
H'100 H'1A0
General FPU disable exception 2
4
(VBR)
H'100 H'800
Slot FPU disable exception
2
4
(VBR)
H'100 H'820
Data address error (read)
2
5
(VBR)
H'100 H'0E0
Data address error (write)
2
5
(VBR)
H'100 H'100
Data TLB miss exception (read) 2
6
(VBR)
H'400 H'040
Data TLB miss exception (write) 2
6
(VBR)
H'400 H'060
Data TLB protection
2
7
(VBR)
H'100 H'0A0
violation exception (read)
Data TLB protection
2
7
(VBR)
H'100 H'0C0
violation exception (write)
FPU exception
2
8
(VBR)
H'100 H'120
Initial page write exception
2
9
(VBR)
H'100 H'080
Rev. 1.00 Oct. 01, 2007 Page 110 of 1956
REJ09B0256-0100