SH7763 Datasheet, PDF (129/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Addressing Instruction
Mode
Format
Effective Address Calculation Method
Calculation
Formula
Immediate #imm:8
8-bit immediate data imm of TST, AND, OR, or —
XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or
—
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction is —
zero-extended and multiplied by 4.
Note:
For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
Rev. 1.00 Oct. 01, 2007 Page 63 of 1956
REJ09B0256-0100