SH7763 Datasheet, PDF (325/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.9 Interrupt mask clear register 1 (INTMSKCLR1)
INTMSKCLR1 is 32-bit write-only registers that clear the mask settings for IRL interrupt
requests. An undefined value is read.
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− ^{IC10 IC11} − − − − − − − − − − − − −
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−−−−−− −−− −−− −−−−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Initial
Bit
Bit Name Value
31
IC10
0
30
IC11
0
29 to 0 
All 0
R/W Description
R/W Clears masking of
[When reading]
IRQ3/IRL3 to IRQ0/IRL0
interrupt requests when
IRL[3:0] are encoded
An undefined value is
read.
interrupt input.
[When writing]
R/W Clears masking of
0: Invalid
IRQ7/IRL7 to IRQ4/IRL4 1: Clears the
interrupt requests when
IRL[7:4] are encoded
corresponding interrupt
mask (Interrupts are
interrupt input.
enabled)
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 259 of 1956
REJ09B0256-0100