SH7763 Datasheet, PDF(441/2026 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7763 Datasheet, PDF (441/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

◁

Section 11 Local Bus State Controller (LBSC)

CLKOUT

A25 to A5

A4 to A0

CSn

RDWR

RD

D31 to D0

(read)

BS

RDY

TAS1 T1 TS1 TB2 TB1 TB2 TB1 TB2 TB1 T2 TH1 TAH1

*

DACK

Note: * When CSnBCR RDSPL is set to 1.

Figure 11.13 Burst ROM Wait Access Timing

11.5.5 PCMCIA Interface

Areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated

in JEIDA specification version 4.2 (PCMCIA 2.1), by setting bits TYPE[2:0] in CS5BCR and

CS6BCR.

Figure 11.14 shows an example of PCMCIA card connection to this LSI. To enable hot insertion

of PCMCIA cards (i.e., insertion or removal while system power is being supplied), a three-state

buffer must be connected between this LSI bus interface and the PCMCIA cards.

Since operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard,

this LSI supports the PCMCIA interface only in little-endian mode through little-endian mode

setting.

PCMCIA interface can select space property from among 8-bit common memory, 16-bit common

memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space,

dynamic I/O bus sizing, and ATA complement mode by setting bits SAA[2:0] and SAB[2:0] in

CSnPCR.

Rev. 1.00 Oct. 01, 2007 Page 375 of 1956

REJ09B0256-0100

▷