SH7763 Datasheet, PDF (800/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 16-Bit Timer Pulse Unit (TPU)
20.4.3 Buffer Operation
Buffer operation, enables TGRC and TGRD to be used as buffer registers.
Table 20.8 shows the register combinations used in buffer operation.
Table 20.8 Register Combinations in Buffer Operation
Timer General Register
TGRA
TGRB
Buffer Register
TGRC
TGRD
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. For update timing from a buffer register, rewriting on
compare match occurrence or on counter cleaning can be selected.
This operation is illustrated in figure 20.8.
Counter cleaning signal
BFWT bit
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 20.8 Compare Match Buffer Operation
Rev. 1.00 Oct. 01, 2007 Page 734 of 1956
REJ09B0256-0100