SH7763 Datasheet, PDF (216/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
MMUCR contents can be changed by software. However, the LRUI and URC bits may also be
updated by hardware.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LRUI
URB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
R R/W R/W R/W R/W R/W R/W R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
URC
SQMD SV
TI
AT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R R/W R R/W
Bit
Bit Name
31 to 26 LRUI
Initial
Value
All 0
R/W Description
R/W Least Recently Used ITLB
These bits indicate the ITLB entry to be replaced. The
LRU (least recently used) method is used to decide
the ITLB entry to be replaced in the event of an ITLB
miss. The entry to be purged from the ITLB can be
confirmed using the LRUI bits.
LRUI is updated by means of the algorithm shown
below. x means that updating is not performed.
000xxx: ITLB entry 0 is used
1xx00x: ITLB entry 1 is used
x1x1x0: ITLB entry 2 is used
xx1x11: ITLB entry 3 is used
xxxxxx: Other than above
When the LRUI bit settings are as shown below, the
corresponding ITLB entry is updated by an ITLB miss.
Ensure that values for which "Setting prohibited" is
indicated below are not set at the discretion of
software. After a power-on or manual reset, the LRUI
bits are initialized to 0, and therefore a prohibited
setting is never made by a hardware update.
x means "don't care".
111xxx: ITLB entry 0 is updated
0xx11x: ITLB entry 1 is updated
x0x0x1: ITLB entry 2 is updated
xx0x00: ITLB entry 3 is updated
Other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 150 of 1956
REJ09B0256-0100