SH7763 Datasheet, PDF (344/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Function
Description
31 to 26 —
All 1 R
These bits are always read as 1. Masks interrupts for
The write value should always each peripheral
be 1.
module.
25
SCIF2 1
R/W Masks SCIF2 interrupts
[When writing]
24
USBF
1
R/W Masks USBF interrupts
0: Invalid
23, 22 —
All 1 R
These bits are always read as 1. ^{1: Interrupts are}
The write value should always
masked
be 1.
[When reading]
21
STIF1 1
R/W Masks STIF1 interrupts
0: No mask setting
20
STIF0 1
R/W Masks STIF0 interrupts
1: Mask setting
19, 18 —
All 1 R
These bits are always read as 1.
The write value should always
be 1.
17
USBH 1
R/W Masks USBH interrupts
16
GETHER 1
R/W Masks GETHER interrupts
15
PCC
1
R/W Masks PCC interrupts
14, 13 —
All 1 R
These bits are always read as 1.
The write value should always
be 1.
12
ADC
1
R/W Masks ADC interrupts
11
TPU
1
R/W Masks TPU interrupts
10
SIM
1
R/W Masks SIM interrupts
9
SIOF2 1
R/W Masks SIOF2 interrupts
8
SIOF1 1
R/W Masks SIOF1 interrupts
7
LCDC 1
R/W Masks LCDC interrupts
6
—
1
R
This bit is always read as 1. The
write value should always be 1.
5
IIC1
1
R/W Masks IIC1 interrupts
4
IIC0
1
R/W Masks IIC0 interrupts
3
SSI3
1
R/W Masks SSI3 interrupts
Rev. 1.00 Oct. 01, 2007 Page 278 of 1956
REJ09B0256-0100