SH7763 Datasheet, PDF(72/2026 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

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SH7763 Datasheet, PDF (72/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

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Section 1 Overview

Item

Local bus state

controller (LBSC)

Features

â¢ Physical address space divided into seven areas (areas 0 to 6), each

comprising up to 64 Mbytes

ï£§ I/F configuration, bus width, and wait cycle insertion are settable for

each area

â¢ SRAM interface

ï£§ Wait cycle insertion by register setting

ï£§ Wait cycle insertion by the RDY pin

ï£§ Supported bus width: 8, 16, or 32 bits

ï£§ Supported space: Areas 0 to 2 and areas 4 to 6

â¢ Burst ROM interface

ï£§ Wait cycle insertion by register setting

ï£§ Number of bursts is specified by register setting

ï£§ Supported bus width: 8, 16, or 32 bits

ï£§ Supported space: Areas 0, 5, and 6

â¢ Interface for SRAM with byte selection

ï£§ Supports direct connection to SRAM with byte selection

ï£§ Supported space: Areas 1 and 4

â¢ PCMCIA interface (only supported in little endian mode)

ï£§ Wait cycle insertion by register setting

ï£§ Supports ATAPI interface (multi-word DMA supported)

ï£§ Supports I/O bus-width sizing

ï£§ Supported space: Areas 5 and 6

Rev. 1.00 Oct. 01, 2007 Page 6 of 1956

REJ09B0256-0100

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