SH7763 Datasheet, PDF (158/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
The parallel execution of two instructions can be carried out under following conditions.
1. Both addr (preceding instruction) and addr+2 (following instruction) are specified within the
minimum page size (1 Kbyte).
2. The execution of these two instructions is supported in table 4.3, Combination of Preceding
and Following Instructions.
3. Data used by an instruction of addr does not conflict with data used by a previous instruction
4. Data used by an instruction of addr+2 does not conflict with data used by a previous
instruction
5. Both instructions are valid
Rev. 1.00 Oct. 01, 2007 Page 92 of 1956
REJ09B0256-0100