SH7763 Datasheet, PDF (1943/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

STn_CLK
ST0M_CLKIO
STn_REQ
ST0M_REQ0
STn_START
ST0M_STARTI
STn_VALID
ST0M_VALIDI
STn_D7_STn_D0
ST0M_D7I_ST0M_D0I
t_STCYC
t_STSTS
t_STVLS
t_STDS
t_STSTH
t_STVLH
t_STDH
Section 43 Electrical Characteristics
t_STRQD
Figure 43.52 STIF Clock Valid Receive Timing
(2) Clock Valid Transmission
Table 43.23 STIF Clock Valid Transmission Signal Timing
Conditions: V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
ST_CLK cycle time
ST_REQ setup time
ST_REQ hold time
ST_START delay time
ST_VALID delay time
ST_DATA delay time
Symbol
t_STCYC
t_STRQS
t_STRQH
t
STSTD
t
STVLD
t
STDD
Min.
30
7
5
3
3
3
Max.
—
—
—
21
21
21
Unit Figure
ns 43.53
ns 43.53
ns 43.53
ns 43.53
ns 43.53
ns 43.53
Rev. 1.00 Oct. 01, 2007 Page 1877 of 1956
REJ09B0256-0100