SH7763 Datasheet, PDF (1530/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
Bit
Bit Name Initial Value R/W Description
5
BLE
0
R/W BulkListEnable
When set, this bit enables processing of the
Bulk list.
4
CLE
0
R/W ControlListEnable
This bit is set to enable the processing of the
control list in the next frame. If cleared by HCD,
the processing of the control list is not carried
out after next SOF. The host controller must
check this bit whenever the list will be
processed. When disabling, HDC can correct
the list. When USBHCCED indicates ED to be
deleted, HCD should hasten the pointer by
updating USBHCCED before re-enabling the list
processing.
0: Control list processing is not carried out
1: Control list processing is carried out
3
IE
0
R/W IsochronousEnable
When clear, this bit disables the Isochronous
List when the Periodic List is enabled (so
Interrupt EDs may be serviced). While
processing the Periodic List, the Host Controller
will check this bit when it finds an isochronous
ED.
2
PLE
0
R/W PeriodicListEnable
When set, this bit enables processing of the
Periodic (interrupt and isochronous) list. The
Host Controller checks this bit prior to
attempting any periodic transfers in a frame.
1, 0
CBSR[1:0] 00
R/W ControlBulkServiceRatio
Specify the number of Control Endpoints
serviced for every Bulk Endpoint. Encoding is
N-1 where N is the number of Control Endpoints
(i.e. '00' = 1 Control Endpoint; '11' = 4 Control
Endpoints)
Rev. 1.00 Oct. 01, 2007 Page 1464 of 1956
REJ09B0256-0100