SH7763 Datasheet, PDF (511/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
MCS
MRAS
MCAS
MWE
MDQS
MDA
MDQM
T0 T1 T2 T3
MRS
*1
*1
*2
Hi-Z
Hi-Z
Notes: 1. Sets the operating mode and other necessary parameters.
2. For mode register setting: BA1 = low, BA0 = low
For extended mode register setting: BA1 = low, BA0 = high
Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS))
Rev. 1.00 Oct. 01, 2007 Page 445 of 1956
REJ09B0256-0100