SH7763 Datasheet, PDF (563/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
1
MWPDI 0
SH: R/WC Master Write PERR Detection Interrupt
PCI: R
Indicates that the PERR signal has been received
during a master write access (only detected when
PCICMD.PER is set to 1) when the PCIC functions as
a master.
0: Master write PERR interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master write PERR interrupt occurs
[Set condition]
When a master write PERR interrupt occurs.
0
MRDPEI 0
SH: R/WC Master Read Data Parity Error Interrupt
PCI: R
Indicates that a data parity error has been detected
during a master read access (only detected when
PCICMD.PER is set to 1) when the PCIC functions as
a master.
0: Master read data perity error interrupt does not
occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master read data perity error interrupt occurs
[Set condition]
When a master read data perity error interrupt occurs.
Rev. 1.00 Oct. 01, 2007 Page 497 of 1956
REJ09B0256-0100