SH7763 Datasheet, PDF (1142/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
1
CKE1
0
R/W Clock Enable 1, 0
0
CKE0
0
R/W These bits select the SCIF clock source and whether to
enable or disable the clock output from the SCIF_SCK
pin. The CKE1 and CKE0 bits are used together to
specify whether the SCIF_SCK pin functions as a serial
clock output pin or a serial clock input pin. Note
however that the CKE0 bit setting is valid only when an
internal clock is selected as the SCIF clock source
(CKE1 = 0). When an external clock is selected (CKE1
= 1), the CKE0 bit setting is invalid. The CKE1 and
CKE0 bits must be set before determining the SCIF's
operating mode with SCSMR.
• Asynchronous mode
00: Internal clock/SCIF_SCK pin functions as port
01: Internal clock/SCIF_SCK pin functions as
clock output*¹
1x: External clock/SCIF_SCK pin functions as
clock input*²
• Clocked synchronous mode
0x: Internal clock/SCIF_SCK pin functions as
synchronization clock output
1x: External clock/SCIF_SCK pin functions as
synchronization clock input
Notes: x: Don't care
1. Outputs a clock with a frequency 16 times the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
Rev. 1.00 Oct. 01, 2007 Page 1076 of 1956
REJ09B0256-0100