SH7763 Datasheet, PDF (595/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
13.4.3 Master Access
This section describes how the PCIC is accessed by software in this LSI and the restrictions on
usage, such as buffering and synchronization with other devices, when the PCIC is used in both
the host bus bridge and normal modes.
(1) Address Space of PCIC
Table 13.5 shows the PCIC address map.
Table 13.5 PCIC Address Map
Physical Address
Memory Area
32-Bit Address
29-Bit Address Mode Extended Mode*
Space Size
PCI memory space1
(Area 4)
H'1000 0000 to
H'13FF FFFF
H'1000 0000 to
H'13FF FFFF
64 Mbytes
PCI memory space 2
—
(Only 32-bit address extended
mode)
H'C000 0000 to
H'DFFF FFFF
512 Mbytes
PCI memory space 0
H'FD00 0000 to
H'FD00 0000 to
16 Mbytes
H'FDFF FFFF
H'FDFF FFFF
Control register
H'FE00 0000 to
H'FE00 0000 to
256 Kbytes
H'FE03 FFFF
H'FE03 FFFF
PCIC internal register
H'FE04 0000 to
H'FE04 0000 to
256 Kbytes
(configuration and local registers) H'FE07 FFFF
H'FE07 FFFF
Reserved
H'FE08 0000 to
H'FE08 0000 to
1.5 Mbytes
H'FE1F FFFF
H'FE1F FFFF
PCI I/O space
H'FE20 0000 to
H'FE20 0000 to
2 Mbytes
H'FE3F FFFF
H'FE3F FFFF
Note: * For details, see section 7.8, Notes on Using 32-Bit Address Extended Mode.
The address space of the PCIC is divided into four main spaces (six spaces, altogether): the control
register space (PCIECR), PCI internal control register (PCI configuration and PCI local registers)
space, I/O space, and PCI memory (PCI memory space 0, PCI memory space 1, and PCI memory
space 2).
Rev. 1.00 Oct. 01, 2007 Page 529 of 1956
REJ09B0256-0100