SH7763 Datasheet, PDF (1260/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Table 29.4 shows the operation in each transfer mode.
Table 29.4 Operation in Each Transfer Mode
Transfer Mode Master/Slave SIOF_SYNC
Bit Delay Control Data Method*
Slave mode 1
Slave
Synchronous pulse SYNCDL bit Slot position
Slave mode 2
Slave
Synchronous pulse
Secondary FS
Master mode 1 Master
Synchronous pulse
Slot position
Master mode 2 Master
L/R
No
Not supported
Note: * The control data method is valid only when the FL bit is specified as B'1xxx. (x: don't
care.)
29.3.2 Clock Select Register (SISCR)
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the
master clock. SISCR can be specified when the bits TRMD[1:0] in SIMDR are specified as B'10
or B'11.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSSEL MSIMM —
BRPS[4:0]
—————
BRDV[2:0]
Initial value: 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R/W R/W R/W R/W R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
MSSEL
1
R/W Master Clock Source Selection
The master clock is the clock source input to the baud
rate generator (prescaler).
0: Uses the input clock signal of the SIOF_MCLK pin as
the master clock
1: Uses Pck0 as the master clock
14
MSIMM
1
R/W Master Clock Direct Selection
0: Uses the output clock of the baud rate generator as
the serial clock
1: Uses the master clock itself as the serial clock
13
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1194 of 1956
REJ09B0256-0100