SH7763 Datasheet, PDF (1542/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.15 HcFrameRemaining Register (USBHFR)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT — — — — — — — — — — — — — — —
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
——
FR[13:0]
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R R R
Bit
31
30 to 14
13 to 0
Bit Name
FRT

FR
Initial Value R/W
0
R
All 0
R
All0
R
Description
FrameRemainingToggle
This bit is loaded with FrameIntervalToggle when
FrameRemaining is loaded.
Reserved
These bits are always read as 0. The write value
should always be 0
FrameRemaining
These bits are the 14-bit down counter used to
time a frame. When the Host Controller is in the
USB OPERATIONAL state, the counter
decrements each 12 MHz clock period. When the
count reaches 0, the end of a frame has been
reached. The counter reloads with FrameInterval
at that time. In addition, the counter reloads when
the Host Controller transitions into USB
OPERATIONAL.
Rev. 1.00 Oct. 01, 2007 Page 1476 of 1956
REJ09B0256-0100