SH7763 Datasheet, PDF (1259/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
7
TXDIZ
0
R/W SIOF_TXD Pin Output when Transmission is Invalid*
0: High output (1 output) when invalid
1: High-impedance state when invalid
Note: Invalid means when disabled, and when a slot
that is not assigned as transmit data or control
data is being transmitted.
6
RCIM
0
R/W Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
SIRCR change.
1: Sets the RCRDY bit in SISTR each time when the
SIRCR receives the control data.
5
SYNCAC 0
R/W SIOF_SYNC Pin Polarity
Valid when the SIOF_SYNC signal is output as a
synchronous pulse.
0: Active-high
1: Active-low
4
SYNCDL 0
R/W Data Pin Bit Delay for SIOF_SYNC Pin
Valid when the SIOF_SYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode. This bit should be set to 1.
0: No bit delay
1: 1-bit delay
Note: * When this bit is cleared to 0 (no bit delay is
selected) in slave mode, the receive data is
sampled at the rising edge of SCK.
3 to 0 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1193 of 1956
REJ09B0256-0100