SH7763 Datasheet, PDF (1078/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.6 Transmit/Receive Packet Count Registers 0, 1 (STIPNR0, STIPNR1)
STIPNR sets the number of packets of the stream data to be transmitted or received.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−−−−− −−− −−
PN[20:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 21 
All 0
20 to 0 PN[20:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Transmit/Receive Packets
These bits set the number of packets for transmission
or reception. An interrupt occurs when the number of
packets actually transmitted or received has reached
the value set in these bits. An interrupt does not occur
when 0 is set in these bits.
Rev. 1.00 Oct. 01, 2007 Page 1012 of 1956
REJ09B0256-0100