SH7763 Datasheet, PDF (327/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
23
IC007
0
22
IC006
0
21
IC005
0
20
IC004
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = HLLL (H'8).
R/W Clears masking of an
interrupt request when
IRL[3:0] = HLLH (H'9).
R/W Clears masking of an
interrupt request when
IRL[3:0] = HLHL (H'A).
R/W Clears masking of an
interrupt request when
IRL[3:0] = HLHH (H'B).
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
19
IC003
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = HHLL (H'C).
18
IC002
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = HHLH (H'D).
17
IC001
0
R/W Clears masking of an
interrupt request when
IRL[3:0] = HHHL (H'E).
16
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
15
IC115
0
14
IC114
0
13
IC113
0
12
IC112
0
R/W Clears masking of an
interrupt request when
IRL[7:4] = LLLL (H'0).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LLLH (H'1).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LLHL (H'2).
R/W Clears masking of an
interrupt request when
IRL[7:4] = LLHH (H'3).
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
Rev. 1.00 Oct. 01, 2007 Page 261 of 1956
REJ09B0256-0100