SH7763 Datasheet, PDF (400/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Register Name
CS2 Bus Control Register
CS4 Bus Control Register
CS5 Bus Control Register
CS6 Bus Control Register
CS0 Wait Control Register
CS1 Wait Control Register
CS2 Wait Control Register
CS4 Wait Control Register
CS5 Wait Control Register
CS6 Wait Control Register
CS5 PCMCIA Control Register
CS6 PCMCIA Control Register
Power-On
Abbreviation Reset
Manual
Reset
Sleep
Standby
CS2BCR
H'7777 7770 H'7777 7770 Retained Retained
CS4BCR
H'7777 7770 H'7777 7770 Retained Retained
CS5BCR
H'7777 7770 H'7777 7770 Retained Retained
CS6BCR
H'7777 7770 H'7777 7770 Retained Retained
CS0WCR
H'7777 770F H'7777 770F Retained Retained
CS1WCR
H'7777 770F H'7777 770F Retained Retained
CS2WCR
H'7777 770F H'7777 770F Retained Retained
CS4WCR
H'7777 770F H'7777 770F Retained Retained
CS5WCR
H'7777 770F H'7777 770F Retained Retained
CS6WCR
H'7777 770F H'7777 770F Retained Retained
CS5PCR
H'7700 0000 H'7700 0000 Retained Retained
CS6PCR
H'7700 0000 H'7700 0000 Retained Retained
11.4.1 Memory Address Map Select Register (MMSELR)
The memory address map select register (MMSELR) is a 32-bit register that selects memory
address maps for areas 2 to 5. This register should be accessed at the address H'FE60 0020 in
longwords. Writing is accepted only when the upper 16-bit data is H'A5A5 to prevent
unintentional writing. The upper 29 bits are always read as 0. This register is initialized by a
power-on reset or a manual reset.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− −−−−−−−−−− −−−−−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − − − − − − − − − − − ^AREASEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R R R R R R R R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 334 of 1956
REJ09B0256-0100