SH7763 Datasheet, PDF (1688/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus cycle interval when the LCDC reads VRAM. When LDLIRNR is set
to a value other than H'00, the LCDC does not access VRAM until clock count of the DDR-
SDRAM matches the value set in LDLIRNR. When LDLIRNR is set to H'00 (initial value), the
LCDC accesses VRAM one clock after the LCDC accessed VRAM.
Bit: 15 14 13 12 11 10 9







Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0

LIRN[7:0]
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
15 to 8 
7 to 0 LIRN[7:0]
Initial Value R/W
All 0
R
All 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
VRAM Read Bus Cycle Interval
Specifies the number of the DDR-SDRAM clock
cycles which can be performed during burst cycles
to read VRAM by LCDC.
H'00: one clock cycle
H'01: one clock cycle
H'02: two clock cycles
:
H'FE: 254 clock cycles
H'FF: 255 clock cycles
Rev. 1.00 Oct. 01, 2007 Page 1622 of 1956
REJ09B0256-0100