SH7763 Datasheet, PDF (564/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(7) PCI Interrupt Mask Register (PCIIMR)
This register is the mask register for PCIIR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
TTA
DIM
—
—
—
—
TMT MDE APE SE DPEI DPEI TAD MAD MW MRD
OIM IM DIM DIM TWM TRM IMM IMM PDIM PEIM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 15 
Initial
Value
All 0
R/W
SH: R
PCI: R
14
TTADIM 0
SH: R/W
PCI: R
13 to 10 
All 0 SH: R
PCI: R
9
TMTOIM 0
SH: R/W
PCI: R
8
MDEIM 0
SH: R/W
PCI: R
7
APEDIM 0
SH: R/W
PCI: R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt Mask
0: PCIIR.TTADI disabled (masked)
1: PCIIR.TTADI enabled (not masked)
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Retry Time Out Interrupt Mask
0: PCIIR.TMTOI disabled (masked)
1: PCIIR. TMTOI enabled (not masked)
Master Function Disable Error Interrupt Mask
0: PCIIR.MDEI disabled (masked)
1: PCIIR.MDEI enabled (not masked)
Address Parity Error Detection Interrupt Mask
0: PCIIR.APEDI disabled (masked)
1: PCIIR.APEDI enabled (not masked)
Rev. 1.00 Oct. 01, 2007 Page 498 of 1956
REJ09B0256-0100