SH7763 Datasheet, PDF (346/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W
31 to 26 —
All 0
R
25
GPIO
0
R/W
24
—
0
R
23
SSI0
0
R/W
22
MMC
0
R/W
21
—
0
R
20
SIOF0 0
R/W
19
PCIC5 0
R/W
18
PCIC4 0
R/W
17
PCIC3 0
R/W
16
PCIC2 0
R/W
15
PCIC1 0
R/W
14
PCIC0 0
R/W
13
12
11 to 9
HAC
CMT
—
0
R/W
0
R/W
All 0
R
8
DMAC 0
R/W
Function
Description
These bits are always read as Clears interrupt
0. The write value should
masking for each
always be 0
peripheral module.
Clears GPIO interrupt
[When writing]
masking
0: Invalid
This bit is always read as 0. _{1: Interrupt mask is}
The write value should always _cleared
be 0
[When reading]
Clears SSI0 interrupt masking
Always 0
Clears MMC interrupt
masking
This bit is always read as 0.
The write value should always
be 0
Clears SIOF0 interrupt
masking
Clears PCIC5 interrupt
masking
Clears PCIC4 interrupt
masking
Clears PCIC3 interrupt
masking
Clears PCIC2 interrupt
masking
Clears PCIC1 interrupt
masking
Clears PCIC0 interrupt
masking
Clears HAC interrupt masking
Clears CMT interrupt masking
These bits are always read as
0. The write value should
always be 0
Clears DMAC interrupt
masking
Rev. 1.00 Oct. 01, 2007 Page 280 of 1956
REJ09B0256-0100