SH7763 Datasheet, PDF (978/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W Description
25
RABT
0
R/W Receive Abort Detect
Indicates that the E-MAC aborts receiving a frame
because of failures during frame reception.
0: Frame reception has not been aborted or no
reception directive
1: Frame reception has been aborted
24
RFCOF
0
R/W Receive Frame Counter Overflow
Indicates that the frame counter in the receive FIFO
has overflowed.
0: Receive frame counter has not overflowed
1: Receive frame counter has overflowed
23

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
22
ECI
0
R
E-MAC Status Register Source
This bit is a read-only bit. When the source of an ECSR
interrupt is cleared, this bit is also cleared.
0: E-MAC status interrupt source has not been detected
1: E-MAC status interrupt source has been detected
21
TC[0]
0
R/W Frame Transmission Complete
Indicates, in combination with the TC[1] bit, that all the
data specified by the transmit descriptor has been
transmitted from the E-MAC. For details, see the
description of the TC[1] bit.
Rev. 1.00 Oct. 01, 2007 Page 912 of 1956
REJ09B0256-0100