SH7763 Datasheet, PDF (140/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Instruction
SETT
SLEEP
STC
SR,Rn
STC
GBR,Rn
STC
VBR,Rn
STC
SSR,Rn
STC
SPC,Rn
STC
SGR,Rn
STC
DBR,Rn
STC
Rm_BANK,Rn
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
SR,@-Rn
GBR,@-Rn
VBR,@-Rn
SSR,@-Rn
SPC,@-Rn
SGR,@-Rn
DBR,@-Rn
Rm_BANK,@-Rn
STS
STS
STS
STS.L
STS.L
STS.L
SYNCO
MACH,Rn
MACL,Rn
PR,Rn
MACH,@-Rn
MACL,@-Rn
PR,@-Rn
TRAPA #imm
Operation
Instruction Code Privileged T Bit New
1→T
0000000000011000 —
1
—
Sleep or standby
0000000000011011 Privileged — —
SR → Rn
0000nnnn00000010 Privileged — —
GBR → Rn
0000nnnn00010010 —
——
VBR → Rn
0000nnnn00100010 Privileged — —
SSR → Rn
0000nnnn00110010 Privileged — —
SPC → Rn
0000nnnn01000010 Privileged — —
SGR → Rn
0000nnnn00111010 Privileged — —
DBR → Rn
0000nnnn11111010 Privileged — —
Rm_BANK → Rn
(m = 0 to 7)
0000nnnn1mmm0010 Privileged — —
Rn – 4 → Rn, SR → (Rn)
0100nnnn00000011 Privileged — —
Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 —
——
Rn – 4 → Rn, VBR → (Rn)
0100nnnn00100011 Privileged —
—
Rn – 4 → Rn, SSR → (Rn)
0100nnnn00110011 Privileged —
—
Rn – 4 → Rn, SPC → (Rn)
0100nnnn01000011 Privileged —
—
Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged —
—
Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged —
—
Rn – 4 → Rn,
Rm_BANK → (Rn)
(m = 0 to 7)
0100nnnn1mmm0011 Privileged — —
MACH → Rn
0000nnnn00001010 —
——
MACL → Rn
0000nnnn00011010 —
——
PR → Rn
0000nnnn00101010 —
——
Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 —
——
Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 —
——
Rn – 4 → Rn, PR → (Rn)
0100nnnn00100010 —
——
Prevents the next instruction
from being issued until
instructions issued before this
instruction have been
completed.
0000000010101011 

New
PC + 2 → SPC, SR → SSR,
#imm << 2 → TRA,
H'160 → EXPEVT,
VBR + H'0100 → PC
11000011iiiiiiii —
——
Rev. 1.00 Oct. 01, 2007 Page 74 of 1956
REJ09B0256-0100